Microlens arrays are optical elements used in CCD or CMOS imagers. Placement of a microlens above an active photodetector allows more light to be collected, increasing the electrical signal strength, thus improving the sensitivity of the image sensor. Methods for making microlens in a cost effective way have been reported in U.S. Pat. No. 5,324,623, granted Jun. 28, 1994 to Tsumori et al. for Microlens forming method, and U.S. Pat. No. 6,163,407, granted Dec. 19, 2000, to Okazaki et al., for Microlens array and method of forming same and solid-state image pickup device and method of manufacturing same. The approach of both these patents is to form the lens shape in photoresist, followed by a dry etch pattern transfer to the lens material. The methods to form lens shapes in photoresist include photoresist reflow and direct patterning, using a grayscale mask. The photoresist reflow method has a fill-factor limitation because merging of neighboring lenses must be avoided.
One method for generating a grayscale mask is by e-beam lithography into a high-energy-beam-sensitive (HEBS) material, as is done by Canyon Material. Inc., however, this process is very slow and expensive when fabricating a large image sensor array.
A technology to fabricate grayscale masks in a cost effective way using silicon rich oxide (SRO) as a light attenuating material has been developed, and disclosed in U.S. patent application Ser. No. 11/588,891, filed Oct. 27, 2006, by Ono et al., for Grayscale Reticle for Precise Control of photoresist Exposure. By forming the SRO layer into the desired lens shapes, and putting the film on a reticle plate for use in a photolithography tool, the exposed pattern printed in the photoresist will have the desired lens shapes and orientations. The photolithographic method of fabricating prototype SRO based grayscale mask is disclosed in the above-cited pending patent application, which describes deposition of SRO on a quartz substrate and subsequent patterning and etching into the desired lens shape, and in U.S. patent application Ser. No. 11/657,258, for Method of Fabricating a Grayscale Mask using SmartCut® Wafer Bonding Process, filed Jan. 24, 2007, and U.S. patent application Ser. No. 11/657,326, for Method of Making a Grayscale Reticle Using Step-Over Lithography for Shaping Microlenses, filed Jan. 24, 2007.
In order for the grayscale mask to be used in a conventional IC fabrication process, it has to be made on a reticle plate having the requisite alignment features so that it can be mounted and used in a photolithographic step and repeat tool (stepper). In the preferred embodiment, a six-inch reticle, made out of a 0.25 inch-thick low thermal expansion, quartz plate, having a rectangular shape, is used in a stepper, whereas conventional IC processing tools use only round wafers. Fabrication of a SRO-based grayscale mask on a square quartz plate in a conventional IC processing facility is not possible without major tool modifications. It is necessary to have a transfer technology that allows the completed SRO-grayscale mask formed on a round wafer to be placed on a square quartz plate.
Wafer bonding technology has been used in the IC industry as one method of fabricating a silicon-on-insulator (SOI) device structure, which in turn facilitates high-performance CMOS technologies. A bonding technique using the Smart Cut® is described in one of the above-cited patent applications, and the Smart Cut® process is described in U.S. Pat. No. 5,374,564, granted Dec. 20, 1994 to Bruel, for Process for the production of thin semiconductor material films. In the Smart Cut® method, H+ or H2 implantation and cleaving, or splitting, is required. It is known, however, that hydrogen implantation places a temperature limitation on subsequent processing steps, which, if the temperature is not minimized, will cause hydrogen aggregation, i.e., blisters. In order to avoid blister generation, the process temperature must be limited, and, as the result of such temperature limitation, the finished IC devices lack the degree of quality which would have been achieved with fabrication at higher temperature.
Furthermore, the splitting or cleaving step at the end of the Smart Cut® technology requires an anneal at about 500° C. This step has the tendency to magnify the existing defects either by increasing size of the defective area, or by increasing defect density. To reduce the defect level generated using the Smart Cut® process, a stringent process control is required, which adds to the cost of ICs fabricated using the Smart Cut® process. In some instances, however, use of the Smart Cut® technique for bonding may be desirable, as described in the above-identified method.